For those familiar with RTEMS, this code lives in libcpu and the design mimics that of the cache manager. The middle layer is just 5 functions:
/* * Initialize the hardware to prepare for * memory protection directives. */ rtems_status_code _CPU_Memory_protection_Initialize( void ); /* * Make sure memory protection permission * is valid for this CPU */ rtems_status_code _CPU_Memory_protection_Verify_permission( rtems_memory_protection_permission permission ); /* * Check if memory protection region size * is valid for this CPU */ rtems_status_code _CPU_Memory_protection_Verify_size( size_t size ); /* * Install (enforce) the memory protection entry mpe */ rtems_status_code _CPU_Memory_protection_Install_MPE( rtems_memory_protection_entry *mpe ); /* * Uninstall the memory protection entry mpe */ rtems_status_code _CPU_Memory_protection_Uninstall_MPE( rtems_memory_protection_entry *mpe );These functions are called via thin wrappers from the high-level API. The install and uninstall entry functions are called iteratively by the higher-level functions that install and uninstall protection domains. The two "verify" functions are used by the high-level API to avoid trying to install invalid entries proactively. The remaining functions interact with the hardware directly to support the memory protection mechanisms.
Next I will briefly explain what each function does in my sparc64 implementation.
- _CPU_Memory_protection_Initialize
- Disables interrupts
- Selectively demaps pages that were loaded during system startup
- Flushes the cache
- Maps new pages for the kernel core services
- Installs exception handlers for MMU misses
- _CPU_Memory_protection_Verify_permission
- Returns true; needs a little refinement.
- _CPU_Memory_protection_Verify_size
- Ensures the size (bounds) is a multiple of the supported TLB page size
- _CPU_Memory_protection_Install_MPE
- Adds a TLB entry for the memory region specified in the MPE
- _CPU_Memory_protection_Uninstall_MPE
- Removes the TLB entry for the specified memory region
I think the low level implementation could be easily implemented in ARM processors with only MPU (Memory Protection Unit ) without the need of MMU unit and paging philosophy .
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